mb/google/guybrush: Update bootblock power-on timings for PCIe

This configures the bootblock portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.

Setting the PCIE Reset happens in coreboot instead of in the FSP.

The Aux reset lines are anded with the PCIe RST line, so both have
to be brought up together.  On v1 of guybrush, the PCIe reset line
also resets EC communication, so it must be brought up immediately on
that version.

BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections.  All available modules
are present after training.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

2 files changed, 21 insertions, 0 deletions

diff --git a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
index ba8514c4c2..8255ba8ebf 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
+++ b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+bootblock-y += gpio.c
 ramstage-y += gpio.c
 
 subdirs-y += ./memory
diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
index 05c1542124..e71ed9d57a 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
@@ -18,6 +18,13 @@ static const struct soc_amd_gpio bid1_gpio_table[] = {
 	PAD_GPI(GPIO_74, PULL_NONE),
 };
 
+/* This table is used by guybrush variant with board version < 2. */
+/* Use AUX Reset lines instead of PCIE_RST for Board Version 1 */
+static const struct soc_amd_gpio bid1_early_gpio_table[] = {
+	/* SD_AUX_RESET_L */
+	PAD_GPO(GPIO_70, HIGH),
+};
+
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 {
 	uint32_t board_version = board_id();
@@ -30,3 +37,16 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 
 	return NULL;
 }
+
+const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
+{
+	uint32_t board_version = board_id();
+	*size = 0;
+
+	if (board_version < 2) {
+		*size = ARRAY_SIZE(bid1_early_gpio_table);
+		return bid1_early_gpio_table;
+	}
+
+	return NULL;
+}