diff options
| author | Rob Barnes <robbarnes@google.com> | 2021-11-08 13:04:18 -0700 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-11-13 00:54:21 +0000 |
| commit | f6e421ffc9ede7ebeb56c0941f07f2f7b8b496a0 (patch) | |
| tree | 2f4670395643476e8d94e8462236ee1e7e7e2406 /src/mainboard/google/guybrush/variants/baseboard | |
| parent | 2bcf99fcc4bbdca7edb6a0c616e0a73649833614 (diff) | |
mb/google/guybrush: Add variant_espi_gpio_table
Add separate gpio table for early eSPI bus init. Remove espi GPIO from
early_gpio_table. This allows for initializing eSPI separately from
other GPIOs. Simplify verstage_mainboard_early_init.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/mainboard/google/guybrush/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/gpio.c | 33 | ||||
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h | 3 |
2 files changed, 24 insertions, 12 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index fb017894a2..6b8c2b7caa 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -206,10 +206,23 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* GSC_SOC_INT_L */ PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + +/* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + +/* Support EC trusted */ + /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ + PAD_GPI(GPIO_91, PULL_NONE), +}; + +static const struct soc_amd_gpio espi_gpio_table[] = { + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* ESPI1_DATA0 */ @@ -222,16 +235,6 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), - -/* Enable UART 0 */ - /* UART0_RXD */ - PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART0_TXD */ - PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - -/* Support EC trusted */ - /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ - PAD_GPI(GPIO_91, PULL_NONE), }; /* Power-on timing requirements: @@ -344,3 +347,9 @@ const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size) *size = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } + +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 955d170910..0dc6c7b4d7 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -40,6 +40,9 @@ const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size); /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); +/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); + bool variant_has_pcie_wwan(void); void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); |