diff options
| author | Matt Papageorge <matthewpapa07@gmail.com> | 2021-07-20 15:09:46 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-24 19:49:45 +0000 |
| commit | 5a2feeda39dfc5090c3a3d3bf5e4d8c0af3c650d (patch) | |
| tree | 30515e62c6ee741960c05fa33ef43e4a22948b05 /src/mainboard/google/guybrush/variants/baseboard | |
| parent | 8baa9dfe1e51b8f00569b8be6d799bf3c2ed53ea (diff) | |
soc/amd/*/chip.h: Correct PSPP Enum Value
It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.
BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.
Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Diffstat (limited to 'src/mainboard/google/guybrush/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 30ebe62ef4..f9a1201d68 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -58,7 +58,7 @@ chip soc/amd/cezanne register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC - register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + register "pspp_policy" = "DXIO_PSPP_BALANCED" register "usb_phy_custom" = "1" register "usb_phy" = "{ |