mb/google/guybrush: Update romstage power-on timings for PCIe

This configures the romstage portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.

The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe
devices out of reset, both need to be brought hign.

BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections.  All available modules
are present after training.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 34 insertions, 0 deletions

diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc
index e6a64a8dca..d8fce0a6eb 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc
@@ -3,6 +3,7 @@ bootblock-y += helpers.c
 
 romstage-y += helpers.c
 romstage-y += tpm_tis.c
+romstage-y += gpio.c
 
 ramstage-y += gpio.c
 ramstage-y += helpers.c
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index dc72cdb5c6..0b418d8b58 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -253,6 +253,29 @@ static const struct soc_amd_gpio sleep_gpio_table[] = {
 	/* TODO: Fill sleep gpio configuration */
 };
 
+/* PCIE_RST needs to be brought high before FSP-M runs */
+static const struct soc_amd_gpio pcie_gpio_table[] = {
+/* Disable all AUX_RESET lines & PCIE_RST */
+	/* WWAN_AUX_RESET_L */
+	PAD_GPO(GPIO_18, HIGH),
+	/* WLAN_AUX_RESET (ACTIVE HIGH) */
+	PAD_GPO(GPIO_29, LOW),
+	/* SSD_AUX_RESET_L */
+	PAD_GPO(GPIO_40, HIGH),
+	/* SD_AUX_RESET_L */
+	PAD_GPO(GPIO_69, HIGH),
+	/* BID>1: Unused TP27; BID==1: SD_AUX_RESET_L */
+	PAD_NC(GPIO_70),
+	/* PCIE_RST0_L */
+	PAD_NFO(GPIO_26, PCIE_RST_L, HIGH),
+};
+
+const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(pcie_gpio_table);
+	return pcie_gpio_table;
+}
+
 const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(bootblock_gpio_table);
@@ -282,6 +305,12 @@ const struct soc_amd_gpio * __weak variant_bootblock_override_gpio_table(size_t
 	return NULL;
 }
 
+const struct soc_amd_gpio * __weak variant_pcie_override_gpio_table(size_t *size)
+{
+	*size = 0;
+	return NULL;
+}
+
 const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(early_gpio_table);
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index f1bbfd3b46..243f7ff884 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -25,6 +25,7 @@ const struct soc_amd_gpio *variant_base_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size);
+const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size);
 
 /* This function provides early GPIO init in early bootblock or psp. */
 const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
@@ -32,6 +33,9 @@ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
 /* This function provides GPIO settings at the end of bootblock. */
 const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size);
 
+/* This function provides GPIO settings before PCIe enumeration. */
+const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size);
+
 /* This function provides GPIO settings before entering sleep. */
 const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);