mb/google/glados: port to FSP 2.0

This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.

The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:

- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT

TODO:
- testing

Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

21 files changed, 171 insertions, 289 deletions

diff --git a/src/mainboard/google/glados/variants/asuka/data.vbt b/src/mainboard/google/glados/variants/asuka/data.vbt
deleted file mode 100644
index 8f2a7b0614..0000000000
--- a/src/mainboard/google/glados/variants/asuka/data.vbt
+++ /dev/null
diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb
index cddb10d11a..27bbebaa57 100644
--- a/src/mainboard/google/glados/variants/asuka/devicetree.cb
+++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb
@@ -60,20 +60,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -100,19 +100,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c
index fdef81c5cd..75e0ea689d 100644
--- a/src/mainboard/google/glados/variants/asuka/variant.c
+++ b/src/mainboard/google/glados/variants/asuka/variant.c
@@ -18,10 +18,13 @@
 #include <string.h>
 #include <baseboard/variant.h>
 #include <fsp/soc_binding.h>
+#include <soc/romstage.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -39,18 +42,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 int is_dual_channel(const int spd_index)
diff --git a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h
index 72eef684b8..45636acad2 100644
--- a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h
+++ b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h
@@ -19,6 +19,6 @@
 
 int is_dual_channel(const int spd_index);
 void mainboard_gpio_smi_sleep(void);
-void variant_memory_init_params(MEMORY_INIT_UPD *memory_params, int spd_index);
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index);
 
 #endif /* GLADOS_VARIANT_H */
diff --git a/src/mainboard/google/glados/variants/caroline/data.vbt b/src/mainboard/google/glados/variants/caroline/data.vbt
deleted file mode 100644
index 02e1cd10f6..0000000000
--- a/src/mainboard/google/glados/variants/caroline/data.vbt
+++ /dev/null
diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb
index aabf179b93..6314af8661 100644
--- a/src/mainboard/google/glados/variants/caroline/devicetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb
@@ -71,20 +71,20 @@ chip soc/intel/skylake
 	register "SlowSlewRateForSa" = "0"	# Fast/2
 	register "FastPkgCRampDisable" = "0"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 4A        | 24A       | 24A         | 24A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -111,19 +111,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c
index ab6bd2c1bd..4338d55602 100644
--- a/src/mainboard/google/glados/variants/caroline/variant.c
+++ b/src/mainboard/google/glados/variants/caroline/variant.c
@@ -21,9 +21,11 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -41,19 +43,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
-	memory_params->DdrFreqLimit = 1600;
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)
diff --git a/src/mainboard/google/glados/variants/cave/data.vbt b/src/mainboard/google/glados/variants/cave/data.vbt
deleted file mode 100644
index 02e1cd10f6..0000000000
--- a/src/mainboard/google/glados/variants/cave/data.vbt
+++ /dev/null
diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb
index 993cab0cee..22ee80f56d 100644
--- a/src/mainboard/google/glados/variants/cave/devicetree.cb
+++ b/src/mainboard/google/glados/variants/cave/devicetree.cb
@@ -70,20 +70,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 4A    | 24A   | 24A         | 24A         | 24A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 4A        | 24A       | 24A         | 24A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -110,19 +110,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c
index d63a298df7..d625f1700a 100644
--- a/src/mainboard/google/glados/variants/cave/variant.c
+++ b/src/mainboard/google/glados/variants/cave/variant.c
@@ -21,9 +21,11 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -41,18 +43,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)
diff --git a/src/mainboard/google/glados/variants/chell/data.vbt b/src/mainboard/google/glados/variants/chell/data.vbt
deleted file mode 100644
index a654a5efd5..0000000000
--- a/src/mainboard/google/glados/variants/chell/data.vbt
+++ /dev/null
diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb
index a3797571ff..5b82e5aaad 100644
--- a/src/mainboard/google/glados/variants/chell/devicetree.cb
+++ b/src/mainboard/google/glados/variants/chell/devicetree.cb
@@ -70,20 +70,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -110,19 +110,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c
index 3e8503fe9e..892dbeed38 100644
--- a/src/mainboard/google/glados/variants/chell/variant.c
+++ b/src/mainboard/google/glados/variants/chell/variant.c
@@ -21,15 +21,18 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
 		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
 		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
 		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+
 	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
 		{ 0, 3, 1, 2, 4, 5, 6, 7 },
@@ -41,18 +44,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)
diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb
index 1d9e6cdf1f..20166253c9 100644
--- a/src/mainboard/google/glados/variants/glados/devicetree.cb
+++ b/src/mainboard/google/glados/variants/glados/devicetree.cb
@@ -70,20 +70,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -110,19 +110,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c
index d63a298df7..d625f1700a 100644
--- a/src/mainboard/google/glados/variants/glados/variant.c
+++ b/src/mainboard/google/glados/variants/glados/variant.c
@@ -21,9 +21,11 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -41,18 +43,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)
diff --git a/src/mainboard/google/glados/variants/lars/data.vbt b/src/mainboard/google/glados/variants/lars/data.vbt
deleted file mode 100644
index 0aac82c3b1..0000000000
--- a/src/mainboard/google/glados/variants/lars/data.vbt
+++ /dev/null
diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb
index b8871d196d..503cf5a58d 100644
--- a/src/mainboard/google/glados/variants/lars/devicetree.cb
+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb
@@ -58,20 +58,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -98,19 +98,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c
index 37860c3738..c24950d814 100644
--- a/src/mainboard/google/glados/variants/lars/variant.c
+++ b/src/mainboard/google/glados/variants/lars/variant.c
@@ -28,9 +28,11 @@
 #define MEM_SINGLE_CHANB	0xb
 #define MEM_SINGLE_CHANC	0xc
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -58,18 +60,12 @@ void variant_memory_init_params(
 	if (spd_index == K4E6E304EB_MEM_ID)
 		targeted_rcomp = StrengthendRcompTarget;
 
-	memcpy(params->DqByteMapCh0, dq_map[0],
-			sizeof(params->DqByteMapCh0));
-	memcpy(params->DqByteMapCh1, dq_map[1],
-			sizeof(params->DqByteMapCh1));
-	memcpy(params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(params->DqsMapCpu2DramCh0));
-	memcpy(params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(params->DqsMapCpu2DramCh1));
-	memcpy(params->RcompResistor, RcompResistor,
-			sizeof(params->RcompResistor));
-	memcpy(params->RcompTarget, targeted_rcomp,
-			sizeof(params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 int is_dual_channel(const int spd_index)
diff --git a/src/mainboard/google/glados/variants/sentry/data.vbt b/src/mainboard/google/glados/variants/sentry/data.vbt
deleted file mode 100644
index 0aac82c3b1..0000000000
--- a/src/mainboard/google/glados/variants/sentry/data.vbt
+++ /dev/null
diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb
index 7f52586e3d..4c6bbf817a 100644
--- a/src/mainboard/google/glados/variants/sentry/devicetree.cb
+++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb
@@ -60,20 +60,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -100,19 +100,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c
index 101be2a0fb..b77e5edc7f 100644
--- a/src/mainboard/google/glados/variants/sentry/variant.c
+++ b/src/mainboard/google/glados/variants/sentry/variant.c
@@ -21,9 +21,11 @@
 
 #define K4E6E304EE_MEM_ID	0x3
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -51,16 +53,10 @@ void variant_memory_init_params(
 	if (spd_index == K4E6E304EE_MEM_ID)
 		targeted_rcomp = StrengthendRcompTarget;
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, targeted_rcomp,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }