diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2018-07-08 19:17:38 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-07-24 12:05:12 +0000 |
commit | ec975b0a4fb1ec6c8633d20cb99e20f71909d40c (patch) | |
tree | c48c3a05955d7b07b78831bd6e8f0cad77fb250a /src/mainboard/google/glados/variants/cave/variant.c | |
parent | 19e7060d7f485ae8f5860f11c7aa26235aaace06 (diff) |
google/cave: Add as a variant of glados
Add google/cave (Asus Chromebook Flip C302SA) as a variant of
glados Skylake reference board:
- add cave-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]
Test: build/boot google/cave, verify correct functionality
Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/glados/variants/cave/variant.c')
-rw-r--r-- | src/mainboard/google/glados/variants/cave/variant.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c new file mode 100644 index 0000000000..2ce0a9001c --- /dev/null +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variant.h> +#include <gpio.h> +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <variant/gpio.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + memcpy(pei_data->RcompResistor, RcompResistor, + sizeof(RcompResistor)); + memcpy(pei_data->RcompTarget, RcompTarget, + sizeof(RcompTarget)); +} + +void mainboard_gpio_smi_sleep(void) +{ + int i; + + /* Power down the rails on any sleep type. */ + gpio_t active_high_signals[] = { + EN_PP3300_KEPLER, + EN_PP3300_DX_TOUCH, + EN_PP3300_DX_EMMC, + EN_PP1800_DX_EMMC, + EN_PP3300_DX_CAM, + }; + + for (i = 0; i < ARRAY_SIZE(active_high_signals); i++) + gpio_set(active_high_signals[i], 0); +} |