diff options
| author | Shelley Chen <shchen@chromium.org> | 2017-06-09 13:05:29 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-20 03:16:51 +0200 |
| commit | 5aa64b97db0577f4ba2e83b36fc41d33453cfb3d (patch) | |
| tree | 3e7acc2cad4203f3e314261948b786f9930bf67b /src/mainboard/google/fizz/gpio.h | |
| parent | db287aad2547d6bc4a710c8a511448b5ff5ebead (diff) | |
google/fizz: Enable cr50 over SPI
By default disabled. Will need to add
FIZZ_USE_SPI_TPM config to enable.
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure that TPM works in verstage
CQ-DEPEND=CL:530184
Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20134
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fizz/gpio.h')
| -rw-r--r-- | src/mainboard/google/fizz/gpio.h | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index 9f7da49ed4..56324b54b0 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -80,10 +80,21 @@ static const struct pad_config gpio_table[] = { /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), /* PCH_SPI_H1_3V3_CS_L */ -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), /* PCH_SPI_H1_3V3_CLK */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), /* PCH_SPI_H1_3V3_MISO */ -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), /* PCH_SPI_H1_3V3_MOSI */ +#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM) +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +#else +/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), +/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +#endif /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ /* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */ /* GSPI1_MISO */ PAD_CFG_GPI(GPP_B21, 20K_PU, DEEP), /* HWA_TRST_N */ @@ -238,6 +249,16 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM) +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +#endif #if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */ |