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authorShelley Chen <shchen@chromium.org>2017-03-10 17:44:00 -0800
committerMartin Roth <martinroth@google.com>2017-03-23 20:46:03 +0100
commit336d8c8cd09f8bd540bc7a0e0f52177c03c4c586 (patch)
tree670b59f8a9c5d96e7fec67f37ebb3cdfb1baa92c /src/mainboard/google/fizz/acpi
parent243dc3913df4bc112e074931c7726a6eb21273c6 (diff)
google/fizz: Remove poppy-specific configs
- Remove spd files/directory - Remove audio blobs - Remove dptf.asl contents - Remove MKBP - Remove acpi table initialization BUG=b:35775024 BRANCH=None TEST=Compiles successfully Change-Id: I5d717d23224956ee1653c5ded28abd05cd254c3a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/18857 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz/acpi')
-rw-r--r--src/mainboard/google/fizz/acpi/dptf.asl83
1 files changed, 0 insertions, 83 deletions
diff --git a/src/mainboard/google/fizz/acpi/dptf.asl b/src/mainboard/google/fizz/acpi/dptf.asl
index f8e5f5c5c7..e69de29bb2 100644
--- a/src/mainboard/google/fizz/acpi/dptf.asl
+++ b/src/mainboard/google/fizz/acpi/dptf.asl
@@ -1,83 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define DPTF_CPU_PASSIVE 94
-#define DPTF_CPU_CRITICAL 99
-
-#define DPTF_TSR0_SENSOR_ID 1
-#define DPTF_TSR0_SENSOR_NAME "Ambient"
-#define DPTF_TSR0_PASSIVE 55
-#define DPTF_TSR0_CRITICAL 70
-
-#define DPTF_TSR1_SENSOR_ID 2
-#define DPTF_TSR1_SENSOR_NAME "Charger"
-#define DPTF_TSR1_PASSIVE 55
-#define DPTF_TSR1_CRITICAL 75
-
-#define DPTF_TSR2_SENSOR_ID 3
-#define DPTF_TSR2_SENSOR_NAME "DRAM"
-#define DPTF_TSR2_PASSIVE 52
-#define DPTF_TSR2_CRITICAL 75
-
-#define DPTF_ENABLE_CHARGER
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
- Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
- Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
- Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
- Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
-})
-
-Name (DTRT, Package () {
- /* CPU Throttle Effect on CPU */
- Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
-
- /* CPU Effect on Temp Sensor 0 */
- Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
-
-#ifdef DPTF_ENABLE_CHARGER
- /* Charger Effect on Temp Sensor 1 */
- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
-#endif
-
- /* CPU Effect on Temp Sensor 2 */
- Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
- 0x2, /* Revision */
- Package () { /* Power Limit 1 */
- 0, /* PowerLimitIndex, 0 for Power Limit 1 */
- 1600, /* PowerLimitMinimum */
- 4500, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 200 /* StepSize */
- },
- Package () { /* Power Limit 2 */
- 1, /* PowerLimitIndex, 1 for Power Limit 2 */
- 3000, /* PowerLimitMinimum */
- 7000, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 1000 /* StepSize */
- }
-})
-
-/* Include DPTF */
-#include <soc/intel/skylake/acpi/dptf/dptf.asl>