diff options
author | Subrata Banik <subratabanik@google.com> | 2024-06-25 00:17:56 +0530 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2024-06-26 22:30:42 +0000 |
commit | 3aea34a9933f7884a2c08b9611f7b3ff9d791b1d (patch) | |
tree | 4de5afb69b07e9db7db5ef700a38d8fdded20ff2 /src/mainboard/google/fatcat/variants/baseboard | |
parent | f3aaa0e1539c16a3a26a769110ec1aca458ab410 (diff) |
mb/google/fatcat: Add minimal code support for fatcat
This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google/fatcat/variants/baseboard')
6 files changed, 181 insertions, 0 deletions
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk new file mode 100644 index 0000000000..be05cd4e5c --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb new file mode 100644 index 0000000000..9f4f345501 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -0,0 +1,3 @@ +chip soc/intel/meteorlake + device domain 0 on end +end diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h new file mode 100644 index 0000000000..b9b46890f1 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <baseboard/gpio.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. AC Connect/Disconnect + * 3. Power button + * 4. Key press + * 5. Mode change + * 6. Low battery + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + MAINBOARD_EC_S5_WAKE_EVENTS) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) | \ + MAINBOARD_EC_S3_WAKE_EVENTS) +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN)) +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable Keyboard Backlight */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ +#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ + +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h new file mode 100644 index 0000000000..67eb97ff73 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* FIXME: update below code as per board schematics */ +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI 0 +/* GPIO IRQ for tight timestamps / wake support */ +#define EC_SYNC_IRQ 0 +/* WP signal to PCH */ +#define GPIO_PCH_WP 0 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c new file mode 100644 index 0000000000..4f621f38ce --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-3.0-or-later */ + +#include <baseboard/variants.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + /* TODO: Add Memory configuration */ + .ect = 1, /* Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + return 0; +} + +bool __weak variant_is_half_populated(void) +{ + return 0; +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..8a97d00deb --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <chip.h> +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of entries for + * each table. + */ + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num); +void fw_config_gpio_padbased_override(struct pad_config *padbased_table); + +const struct mb_cfg *variant_memory_params(void); +void variant_get_spd_info(struct mem_spd *spd_info); +int variant_memory_sku(void); +bool variant_is_half_populated(void); +void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config); + +/* Get soc power limit config struct for current CPU sku */ +struct soc_power_limits_config *variant_get_soc_power_limit_config(void); + +enum s0ix_entry { + S0IX_EXIT, + S0IX_ENTRY, +}; + +void variant_generate_s0ix_hook(enum s0ix_entry entry); + +/* Modify devictree settings during ramstage by baseboard */ +void baseboard_devtree_update(void); +/* Modify devictree settings during ramstage by dedicated variant */ +void variant_devtree_update(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */ |