diff options
| author | Saurabh Mishra <mishra.saurabh@intel.com> | 2024-09-17 14:52:59 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-10-03 03:37:07 +0000 |
| commit | 362cc976fb498435f94b8d982c33a54b1dd7ab56 (patch) | |
| tree | 11b336f2b95a9dbac5b06ca887a1a112c47e41b0 /src/mainboard/google/fatcat/dsdt.asl | |
| parent | 6042ba010a181acc94c7d947158bc52184f03d7e (diff) | |
mb/google/fatcat: Add Panther Lake SOC support
- This patch update the original google/fatcat support added
with Meteor Lake support as a workaround.
- Add initial support to build google/fatcat for Panther Lake SOC
- Add soc acpi file entry in mainboard dsdt.asl
BUG=b:348678529
TEST=Build google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fatcat/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/fatcat/dsdt.asl | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/src/mainboard/google/fatcat/dsdt.asl b/src/mainboard/google/fatcat/dsdt.asl index 2c714d7a0c..03882c6327 100644 --- a/src/mainboard/google/fatcat/dsdt.asl +++ b/src/mainboard/google/fatcat/dsdt.asl @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <variant/ec.h> +#include <variant/gpio.h> DefinitionBlock( "dsdt.aml", @@ -9,8 +10,33 @@ DefinitionBlock( ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 + 0x20240917 ) { - /* TODO: Add ACPI code as per board design */ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/pantherlake/acpi/southbridge.asl> + #include <soc/intel/pantherlake/acpi/tcss.asl> + } + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* ChromeOS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> } |