mb/google/{poppy,eve,fizz}: Configure GPIOs in mainboard chip->init()

mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().

Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 8 insertions, 24 deletions

diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc
index d853404a45..d137f92b2d 100644
--- a/src/mainboard/google/eve/Makefile.inc
+++ b/src/mainboard/google/eve/Makefile.inc
@@ -23,7 +23,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-y += mainboard.c
-ramstage-y += ramstage.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 
 smm-y += smihandler.c
diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c
index 9b9ccdd05f..aceb7b7f6d 100644
--- a/src/mainboard/google/eve/mainboard.c
+++ b/src/mainboard/google/eve/mainboard.c
@@ -21,6 +21,8 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/nhlt.h>
 
+#include "gpio.h"
+
 #define SUBSYSTEM_ID 0x1AE0006B
 
 static const char *oem_id_maxim = "GOOGLE";
@@ -74,6 +76,12 @@ static void mainboard_enable(struct device *dev)
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 }
 
+static void mainboard_chip_init(void *chip_info)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
 struct chip_operations mainboard_ops = {
+	.init = mainboard_chip_init,
 	.enable_dev = mainboard_enable,
 };
diff --git a/src/mainboard/google/eve/ramstage.c b/src/mainboard/google/eve/ramstage.c
deleted file mode 100644
index be3676a1f2..0000000000
--- a/src/mainboard/google/eve/ramstage.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Google Inc.
- * Copyright (C) 2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/ramstage.h>
-#include "gpio.h"
-
-void mainboard_silicon_init_params(FSP_SIL_UPD *params)
-{
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}