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authorFurquan Shaikh <furquan@google.com>2019-10-23 11:14:23 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-10-25 06:55:22 +0000
commit514ddef4e51c3f9ec1747764e438b570e6725864 (patch)
tree6fe6ecd4b3b37b4b9f701d0a1eb4f5a6e29880de /src/mainboard/google/drallion
parentfb9f320d810b82790ecbaeeb8671c723f433e904 (diff)
mb/google/{drallion,sarien}: Configure GPIOs in mainboard chip->init()
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Change-Id: I5cd89c6e24b6a4b0c20fd476915f3781a0d46e0d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36269 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion')
-rw-r--r--src/mainboard/google/drallion/ramstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c
index b3bf10296a..6d3ebb46cb 100644
--- a/src/mainboard/google/drallion/ramstage.c
+++ b/src/mainboard/google/drallion/ramstage.c
@@ -66,7 +66,7 @@ static const struct pad_config gpio_unused[] = {
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
};
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+static void mainboard_init(void *chip_info)
{
const struct pad_config *gpio_table;
size_t num_gpios;
@@ -85,5 +85,6 @@ static void mainboard_enable(struct device *dev)
}
struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
.enable_dev = mainboard_enable,
};