diff options
| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2019-09-09 14:05:33 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-18 12:55:16 +0000 |
| commit | 86f29118d37d0fa35ed5e20668336f852cd12550 (patch) | |
| tree | 15aad9d482ca7845f803c59f0e579545712ce292 /src/mainboard/google/drallion/romstage.c | |
| parent | 95f8359093c37906cc277e4e850743e19b415c7e (diff) | |
mb/google/drallion: Enable 360 sensor detection
Implementing logic to detect SKU model and enable ISH accordignly.
BUG=b:140748790
Change-Id: I22fafb43dce6545851883be556a02d65a01fc386
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35303
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion/romstage.c')
| -rw-r--r-- | src/mainboard/google/drallion/romstage.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f34b..c9f009e599 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -16,6 +16,9 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <baseboard/variants.h> + +void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {} static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -57,6 +60,8 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + variant_mainboard_post_init_params(memupd); + wilco_ec_romstage_init(); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); |