From 86f29118d37d0fa35ed5e20668336f852cd12550 Mon Sep 17 00:00:00 2001
From: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Date: Mon, 9 Sep 2019 14:05:33 -0700
Subject: mb/google/drallion: Enable 360 sensor detection

Implementing logic to detect SKU model and enable ISH accordignly.

BUG=b:140748790

Change-Id: I22fafb43dce6545851883be556a02d65a01fc386
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35303
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/drallion/romstage.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/mainboard/google/drallion/romstage.c')

diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index 20eee7f34b..c9f009e599 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -16,6 +16,9 @@
 #include <ec/google/wilco/romstage.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <baseboard/variants.h>
+
+void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {}
 
 static const struct cnl_mb_cfg memcfg = {
 	/* Access memory info through SMBUS. */
@@ -57,6 +60,8 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	variant_mainboard_post_init_params(memupd);
+
 	wilco_ec_romstage_init();
 
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
-- 
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