diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-07-11 12:07:51 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-27 09:00:49 +0000 |
| commit | 3a14338625d6ae7c6c4e8ee0b1e9be285593b3a6 (patch) | |
| tree | 75e78040495541302dbc483bd87a36d51981b8d3 /src/mainboard/google/dragonegg/chromeos.fmd | |
| parent | 13415333fedada138515a986afab799ca05a785f (diff) | |
mb/google/dragonegg: Add initial mainboard code support
This patch includes support for both ICL ES0 and ES1 samples.
Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md
TEST=Able to build and boot dragonegg.
Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/dragonegg/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/dragonegg/chromeos.fmd | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd new file mode 100644 index 0000000000..07a6987405 --- /dev/null +++ b/src/mainboard/google/dragonegg/chromeos.fmd @@ -0,0 +1,42 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x3F0000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x36F000 + } + SI_BIOS@0x1400000 0xC00000 { + RW_SECTION_A@0x0 0x2d0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x2bffc0 + RW_FWID_A@0x2cffc0 0x40 + } + RW_SECTION_B@0x2d0000 0x2d0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x2bffc0 + RW_FWID_B@0x2cffc0 0x40 + } + RW_MISC@0x5a0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0x5d0000 0x200000 + WP_RO@0x7d0000 0x430000 { + RO_VPD@0x0 0x4000 + RO_SECTION@0x4000 0x42c000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x33c000 + } + } + } +} |