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authorMichael Niewöhner <foss@mniewoehner.de>2022-01-08 20:47:11 +0100
committerPaul Fagerburg <pfagerburg@chromium.org>2022-01-14 00:29:38 +0000
commit45b6080561748fe579c8ee901811cf4043383c2f (patch)
treeb9f37ad3e3962571401fafa2578788f0feb27d5a /src/mainboard/google/deltaur/variants/baseboard
parent9f0285b6fe46d6ec76faad0c099239c227e5caa1 (diff)
soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/deltaur/variants/baseboard')
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index 067222440c..f5dc01910d 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -50,6 +50,7 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1"
register "PcieClkSrcUsage[2]" = "8"
register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieRpSlotImplemented[8]" = "1"
# Mark unused SRCCLKREQs as so
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"