diff options
author | Bora Guvendik <bora.guvendik@intel.com> | 2020-03-09 18:20:07 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-30 08:43:09 +0000 |
commit | 3a1a037231ddb5cdc03d0e147c2335de0f1c8ad6 (patch) | |
tree | 9b1f982991edb60eac011f3824ebb4d4bcf244da /src/mainboard/google/deltaur/chromeos.fmd | |
parent | 97bd2a7f33a784b63b8ede4efc23f39d4dfce37b (diff) |
mb/google/deltaur: add deltaur mainboard initial support
Created a new Google baseboard using Tiger Lake named deltaur, taking
volteer as a starting point.
BUG=b:151102807
TEST=make build successful
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/deltaur/chromeos.fmd')
-rw-r--r-- | src/mainboard/google/deltaur/chromeos.fmd | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd new file mode 100644 index 0000000000..d0cf8e92f8 --- /dev/null +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -0,0 +1,48 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x604000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_ME@0x101000 0x4ff000 + SI_PDR(PRESERVE)@0x600000 0x4000 + } + SI_BIOS@0x604000 0x19fc000 { + RW_DIAG@0x0 0x10cc000 { + RW_LEGACY(CBFS)@0x0 0x10bc000 + DIAG_NVRAM@0x10bc000 0x10000 + } + RW_SECTION_A@0x10cc000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x134c000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x15cc000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + WP_RO@0x15fc000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3ec000 + } + } + } +} |