diff options
| author | Tony Huang <tony-huang@quanta.corp-partner.google.com> | 2021-01-18 10:04:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-19 09:03:24 +0000 |
| commit | fc63f8d5a955c02c7621ba981b7e5594166f6c21 (patch) | |
| tree | 1645465403229410a363b26292fbd38552785e35 /src/mainboard/google/dedede/variants | |
| parent | 91a4512adfe37438b193c3c982e06ec21f75edc4 (diff) | |
mb/google/dedede/var/lantis: Update DPTF parameters
DPTF paramerters from thermal team.
1. PL1 max =5.8W
2. PL1 min =3.8W
3. PL2 =20W
BUG=b:177249297
BRANCH=dedede
TEST=build image and verified by thermal team.
Change-Id: I19654b65613817ebecf979ce7ac4f76d370ebdc2
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants')
| -rw-r--r-- | src/mainboard/google/dedede/variants/lantis/overridetree.cb | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index 297a5c0a97..18d654f5c6 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -60,7 +60,49 @@ chip soc/intel/jasperlake }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000), + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + }" + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3800, + .max_power = 5800, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on |