diff options
| author | MAULIK V VAGHELA <maulik.v.vaghela@intel.com> | 2021-08-02 17:23:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-08-09 06:13:21 +0000 |
| commit | a5a862b39784a41c61965e0579ec8dedba7ebe32 (patch) | |
| tree | 4d1f63f6cade1dc43ec571e8af724d705cc3c08d /src/mainboard/google/dedede/variants | |
| parent | 3c0ecd57c174b7391c66d22406effe18ce570cac (diff) | |
mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC ID
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cb5321c773..38b1da2712 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -27,9 +27,7 @@ fw_config end chip soc/intel/jasperlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this |