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authorTony Huang <tony-huang@quanta.corp-partner.google.com>2022-06-08 14:36:32 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-06-09 16:06:45 +0000
commit8a7ea4586248a6fb8f8f375cf2beb29cd18926e1 (patch)
treef2f6751e1da56a145b89fe02837d889669914ecb /src/mainboard/google/dedede/variants/shotzo/overridetree.cb
parentac4648114c35b2af8e6129132be08683a576f37c (diff)
mb/google/dedede: Create shotzo variant
Create the shotzo variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=b:235303242 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SHOTZO Change-Id: Ia3dc9ea6d1b369b54a966ad86f1531305b8a7f57 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65014 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/shotzo/overridetree.cb')
-rw-r--r--src/mainboard/google/dedede/variants/shotzo/overridetree.cb42
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
new file mode 100644
index 0000000000..404024b1d6
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb
@@ -0,0 +1,42 @@
+chip soc/intel/jasperlake
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | Trackpad |
+ #| I2C1 | Digitizer |
+ #| I2C2 | Touchscreen |
+ #| I2C3 | Camera |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
+ device domain 0 on
+ device pci 15.0 on end
+ end
+end