diff options
| author | Robert Chen <robert.chen@quanta.corp-partner.google.com> | 2024-11-05 21:00:20 -0500 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2024-11-08 01:03:02 +0000 |
| commit | 8d3f419cbc345884aedd7a2f9c1b5bcf378dcefd (patch) | |
| tree | 4def03c3fd8ab586a9b0c670e2cedff21b40ac23 /src/mainboard/google/dedede/variants/drawcia | |
| parent | 0714d5cc8a6c7a8bad4f0a3e605e3a576f32502e (diff) | |
mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.
BUG=b:377400590
TEST=Tested on Drawman with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2
BRANCH=firmware-dedede-13606.B
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85011
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/drawcia')
| -rw-r--r-- | src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 67c9262007..6c745d9f97 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -7,6 +7,9 @@ fw_config end chip soc/intel/jasperlake + # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera |