diff options
| author | Nico Huber <nico.h@gmx.de> | 2024-01-12 16:22:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-19 13:18:17 +0000 |
| commit | 3d80d14cd4ed82e74057cea884dcb9bb7588c076 (patch) | |
| tree | 2b871fd211af0a239a0926f28c787e3cd406cc90 /src/mainboard/google/dedede/variants/dibbi | |
| parent | 9bf38c7d672dbfe0771a15574a7e0c59f38c139c (diff) | |
soc/intel/jasperlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/dibbi')
| -rw-r--r-- | src/mainboard/google/dedede/variants/dibbi/overridetree.cb | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index 5bc127dc58..c7d6afb495 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -38,19 +38,14 @@ chip soc/intel/jasperlake .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" |