diff options
| author | Amanda Huang <amanda_hwang@compal.corp-partner.google.com> | 2023-02-23 17:21:42 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-27 16:44:31 +0000 |
| commit | bd86b0c2f71bf9d04b23519147c49a2f6ec35d6e (patch) | |
| tree | 3d6438055ac97c310008f49716179b780c0ba150 /src/mainboard/google/dedede/variants/dibbi/overridetree.cb | |
| parent | 3267687978b5d2c61a7306701e85d1e801baeeeb (diff) | |
mb/google/dedede/var/dibbi: Improve USB2 strength
BUG=b:269786649
TEST=build and test USB2 port function works fine
BRANCH=dedede
Change-Id: I63928a0d8ce6b2365250fd96572f4a2db948c19d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/dibbi/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/dibbi/overridetree.cb | 44 |
1 files changed, 40 insertions, 4 deletions
diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index 69307a3946..8e7a993e0d 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -49,10 +49,46 @@ chip soc/intel/jasperlake register "DdiPortADdc" = "1" # USB Port Configuration - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A0 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A1 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A2 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A3 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # PL2303 register "usb3_ports[1]" = "USB3_PORT_EMPTY" # No USB3/2 Type-C Port C1 |