diff options
| author | Sunwei Li <lisunwei@huaqin.corp-partner.google.com> | 2021-09-10 16:01:30 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-16 15:38:51 +0000 |
| commit | 50ba6dfec844a750231b1d71bb4d0b9edf6543f9 (patch) | |
| tree | 18f7b5ec3ace509afe030d7a66eb7a07da625d10 /src/mainboard/google/dedede/variants/cappy2/overridetree.cb | |
| parent | 86f0df4ca20bf69e773da2656d5526e4bf8aa076 (diff) | |
mb/google/dedede/var/cappy2: Add USB2 PHY parameters
This change adds fine-tuned USB2 PHY parameters for cappy2.
BUG=b:199485217
TEST=Built and verified USB2 eye diagram test result
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I2aac29e8bba0bf3eff91898ded7561b6211af789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/cappy2/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/cappy2/overridetree.cb | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb index 7e95edae0a..ed0defe298 100644 --- a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb @@ -44,7 +44,30 @@ chip soc/intel/jasperlake register "disable_external_bypass_vr" = "1" # Does not support external vnn power rail # USB Port Configuration - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Camera device domain 0 on device pci 14.0 on |