diff options
| author | Simon Yang <simon1.yang@intel.com> | 2022-04-22 14:07:16 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 17:15:13 +0000 |
| commit | dec327b03b2fbf6dc6f89599107f645ed6a5396f (patch) | |
| tree | 5ab8728acb148be9d573416575c3f91f38a8b1c7 /src/mainboard/google/dedede/variants/bugzzy | |
| parent | 19788cd9a48b7ab302c50a2fd6818a172615d1e5 (diff) | |
soc/intel/jasperlake: Revert CdClock setting
Revert CdClock setting and use default value 0xff.
Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.
BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"
Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/bugzzy')
| -rw-r--r-- | src/mainboard/google/dedede/variants/bugzzy/overridetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index 30e5e454dc..7496428cf7 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -2,9 +2,6 @@ chip soc/intel/jasperlake # MIPI display panel register "DdiPortAConfig" = "2" # DdiPortMipiDsi - # Core Display Clock Frequency selection - register "cd_clock" = "CD_CLOCK_172_8_MHZ" - # Enable Acoustic noise mitigation and set slew rate to 1/8 # Rest of the parameters are 0 by default. register "AcousticNoiseMitigation" = "1" |