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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-05 14:46:14 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-04-27 13:04:23 +0000 |
| commit | 66538e08770794b4bf7baadc53f167a405b870bc (patch) | |
| tree | 1a6dfe2b130da11be878e91bb2f4230f3d7d0c8c /src/mainboard/google/dedede/variants/baseboard/gpio.c | |
| parent | e69461dc25193bc792ba50b7d48081bdccd6e066 (diff) | |
cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.
This fixes building when some debug options are enabled.
Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/gpio.c')
0 files changed, 0 insertions, 0 deletions