diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-07-31 16:53:43 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-02 10:53:46 +0000 |
| commit | eb7940d8b01111c961958a720c74ce3c6707b1ba (patch) | |
| tree | 8c32e7dff5b04d312d1b2ff3d268b2766bba7990 /src/mainboard/google/cyan/variants/ultima | |
| parent | 0aa52739dd7ddb6f1f0ca51cef57b8ccd3f0b5b2 (diff) | |
google/cyan: Mask Audio IRQ on boot
Adapted from chromium commit cf18ab6
[Strago: mask Audio IRQ on boot]
Do not start with audio interrupt unmasked; this causes interrupt storms
on newer kernels that no longer mask all interrupts when initializing
Cherryview pincontrol driver.
TEST=Boot various cyan boards with kernels 3.18 and 4.14;
verify everything works.
Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894688
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/cyan/variants/ultima')
| -rw-r--r-- | src/mainboard/google/cyan/variants/ultima/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index 4e4f0f637c..c6875b4ef2 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -139,7 +139,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ |