diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-20 17:56:48 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-09-16 22:31:32 +0000 |
commit | 4f20a4ae47492fc86293f1c6aed063177992fbaf (patch) | |
tree | 0fdb68c963612f0b4cbc901efbf04293719b9ea2 /src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h | |
parent | 7427abce07fb80289646b7653242022182b9e8f9 (diff) |
google/edgar: add new board as variant of cyan baseboard
Add support for google/edgar (Acer Chromebook 14 CB3-431) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new edgar variant
- Add common code to the baseboard which will apply to all
variants other than cyan
Sourced from Chromium branch firmware-edgar-7287.167.B,
commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data
Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h')
-rw-r--r-- | src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h new file mode 100644 index 0000000000..d68aa13e01 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/cyan/irqroute.h> + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* KBD: Gpio index in N bank */ +#define BOARD_I8042_GPIO_INDEX 17 +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 95 +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define BOARD_TRACKPAD_GPIO_INDEX 18 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5650" +#define AUDIO_CODEC_CID "10EC5650" +#define AUDIO_CODEC_DDN "RTEK Codec Controller " +#define AUDIO_CODEC_I2C_ADDR 0x1A + +/* I2C data hold time */ +#define BOARD_I2C6_DATA_HOLD_TIME 0x2F + +#define DPTF_CPU_PASSIVE 88 +#define DPTF_CPU_CRITICAL 90 + +#endif |