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| author | Elyes Haouas <ehaouas@noos.fr> | 2024-03-23 15:29:37 +0100 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-03-30 07:45:40 +0000 |
| commit | c55765d6818534236338539101630448f00d1595 (patch) | |
| tree | f6e54d36cc3e7ce01e7677b8e234bbd3b4886f7e /src/mainboard/google/cyan/variants/celes | |
| parent | 4709d7c028cccfc4b47b03053965d459b320ad25 (diff) | |
mb/google: Remove blank lines before '}' and after '{'
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/celes')
| -rw-r--r-- | src/mainboard/google/cyan/variants/celes/ramstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index a126a4881a..a28783817c 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -5,7 +5,6 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { - //Follow Intel recommendation to set //BSW D-stepping PERPORTRXISET 2 (low strength) params->Usb2Port0PerPortPeTxiSet = 7; |