mainboard/google: Add Braswell based Cyan board

Add initial files for the cyan board.
Matches chromium tree at 927026db

This board uses the Braswell FSP 1.1 image and does not build
without the FspUpdVpd.h file.

BRANCH=none
BUG=None
Test=Build and run on cyan

Change-Id: I935839be033c25e197e78fbee306104b4162a99a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10182
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

5 files changed, 494 insertions, 0 deletions

diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl
new file mode 100644
index 0000000000..4ba385742a
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/chromeos.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/*
+ * Fields are in the following order.
+ * - Type: recovery = 1 developer mode = 2 write protect = 3
+ * - Active Level - if -1 not a valid gpio
+ * - GPIO number encoding - if -1 not a valid gpio
+ * - Chipset Name
+ *
+ * Note: We need to encode gpios within the 4 separate banks
+ * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded
+ * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
+ */
+
+Name(OIPG, Package() {
+	/* No physical recovery button */
+	Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
+	Package () { 0x0003, 1, 0x10016, "Braswell" },
+})
diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl
new file mode 100755
index 0000000000..4b85449944
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/dptf.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2105 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 1 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		6200,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
+
+/* Include DPTF */
+#include <acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl
new file mode 100644
index 0000000000..16f515c7b4
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/ec.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2105 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* mainboard configuration */
+#include <ec.h>
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl
new file mode 100755
index 0000000000..34b345e574
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/mainboard.asl
@@ -0,0 +1,305 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <onboard.h>
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+		Method (_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+			Return (\LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+		Name (_UID, 1)
+	}
+}
+
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
+Scope (\_SB.I2C1)
+{
+	Device (ETSA)
+	{
+		Name (_HID, "ELAN0001")
+		Name (_DDN, "Elan Touchscreen ")
+		Name (_UID, 5)
+		Name (ISTP, 0) /* TouchScreen */
+
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(BUF0,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					0x10,                     /* SlaveAddress */
+					ControllerInitiated,      /* SlaveMode */
+					400000,                   /* ConnectionSpeed */
+					AddressingMode7Bit,       /* AddressingMode */
+					"\\_SB.I2C1",             /* ResourceSource */
+				)
+				GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+					 "\\_SB.GPSW") { BOARD_TOUCH_GPIO_INDEX }
+
+			} )
+			Name(BUF1,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					0x10,                     /* SlaveAddress */
+					ControllerInitiated,      /* SlaveMode */
+					400000,                   /* ConnectionSpeed */
+					AddressingMode7Bit,       /* AddressingMode */
+					"\\_SB.I2C1",             /* ResourceSource */
+				)
+				GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+					 "\\_SB.GPNC") { BOARD_EVT_TOUCH_GPIO_INDEX }
+
+			} )
+			If (LEqual (\BDID, BOARD_EVT)) {
+				Return (BUF1)
+			} Else {
+				Return (BUF0)
+			}
+		}
+
+		Method (_STA)
+		{
+			If (LEqual (\S1EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
+
+Scope (\_SB.I2C2)
+{
+	/* Maxim Audio Codec */
+	Device (MAXM)   /* Audio Codec driver I2C */
+	{
+		Name (_ADR, 0)
+		Name (_HID, AUDIO_CODEC_HID)
+		Name (_CID, AUDIO_CODEC_CID)
+		Name (_DDN, AUDIO_CODEC_DDN)
+		Name (_UID, 1)
+
+		/* Add DT style bindings with _DSD */
+		Name (_DSD, Package () {
+			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+				/* set maxim micbias to 2.8v */
+				Package () { "maxim,micbias", 3 },
+			}
+		})
+
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(SBUF,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					AUDIO_CODEC_I2C_ADDR,	/* SlaveAddress: bus address */
+					ControllerInitiated,	/* SlaveMode: default to ControllerInitiated */
+					400000,			/* ConnectionSpeed: in Hz */
+					AddressingMode7Bit,	/* Addressing Mode: default to 7 bit */
+					"\\_SB.I2C2",		/* ResourceSource: I2C bus controller name */
+				)
+
+				GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+					"\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
+			} )
+			Return (SBUF)
+		}
+
+		Method (_STA)
+		{
+			If (LEqual (\S2EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+	}
+	Device (TISW)   /* TI Switch driver I2C */
+	{
+		Name (_ADR, 0)
+		Name (_HID, TI_SWITCH_HID)
+		Name (_CID, TI_SWITCH_CID)
+		Name (_DDN, TI_SWITCH_DDN)
+		Name (_UID, 1)
+
+		/* Add DT style bindings with _DSD */
+		Name (_DSD, Package () {
+			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+				/* set ti micbias to 2.8v */
+				Package () { "ti,micbias", 7 },
+			}
+		})
+
+		Method(_CRS, 0x0, NotSerialized)
+		{
+			Name(SBUF,ResourceTemplate ()
+			{
+				I2CSerialBus(
+					TI_SWITCH_I2C_ADDR,	/* SlaveAddress: bus address */
+					ControllerInitiated,	/* SlaveMode: default to ControllerInitiated */
+					400000,	/* ConnectionSpeed: in Hz */
+					AddressingMode7Bit,	/* Addressing Mode: default to 7 bit */
+					"\\_SB.I2C2",	/* ResourceSource: I2C bus controller name */
+				)
+
+				GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+					"\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX }
+
+			} )
+			Return (SBUF)
+		}
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
+
+Scope (\_SB.I2C5)
+{
+	Device (ALSI)
+	{
+		/*
+		 * TODO(dlaurie): Need official HID.
+		 *
+		 * The current HID is created from the Intersil PNP
+		 * Vendor ID "LSD" and a shortened device identifier.
+		 */
+		Name (_HID, EisaId ("LSD2918"))
+		Name (_DDN, "Intersil 29018 Ambient Light Sensor")
+		Name (_UID, 1)
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				0x44,                     /* SlaveAddress */
+				ControllerInitiated,      /* SlaveMode */
+				400000,                   /* ConnectionSpeed */
+				AddressingMode7Bit,       /* AddressingMode */
+				"\\_SB.I2C5",             /* ResourceSource */
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_ALS_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S5EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+	}
+}
+
+Scope (\_SB.I2C6)
+{
+	Device (ETPA)
+	{
+		Name (_HID, "ELAN0000")
+		Name (_DDN, "Elan Touchpad")
+		Name (_UID, 3)
+		Name (ISTP, 1) /* Touchpad */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				0x15,                     /* SlaveAddress */
+				ControllerInitiated,      /* SlaveMode */
+				400000,                   /* ConnectionSpeed */
+				AddressingMode7Bit,       /* AddressingMode */
+				"\\_SB.I2C6",             /* ResourceSource */
+			)
+			GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+				 "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX }
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S6EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
+
+Scope (\_SB.LPEA)
+{
+	Name (GBUF, ResourceTemplate ()
+	{
+		/* Jack Detect (index 0) */
+		GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+			"\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
+	})
+}
+
+Scope (\_SB.GPNC)
+{
+	Method (_AEI, 0, NotSerialized)  // _AEI: ACPI Event Interrupts
+	{
+		Name (RBUF, ResourceTemplate ()
+		{
+			GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+				"\\_SB.GPNC") { BOARD_SCI_GPIO_INDEX }
+		})
+		Return (RBUF)
+	}
+
+	Method (_E0F, 0, NotSerialized)  // _Exx: Edge-Triggered GPE
+	{
+	}
+}
diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl
new file mode 100755
index 0000000000..abc1bf67b4
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/superio.asl
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* mainboard configuration */
+#include <ec.h>
+#include <onboard.h>
+
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+/* Override default IRQ settings */
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\
+                                                     BOARD_I8042_IRQ}
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>