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authorMeera Ravindranath <meera.ravindranath@intel.com>2021-11-11 18:02:13 +0530
committerFelix Singer <felixsinger@posteo.net>2021-11-15 10:34:44 +0000
commit3b037989537bd45350a41c5ae523f51aa44b492f (patch)
tree4c08ccde8b69eabc67665909d9bbdbb4e24c470c /src/mainboard/google/corsola
parentf005c34172413e41e85051a945ca6b0aaccc2c46 (diff)
soc/intel/alderlake: Disable VT-d for early silicons
VT-d needs to disabled for early silicons as it results in a CPU hard hang. BUG=b:197177091 Test=Boot brya to OS with no hang Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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