diff options
| author | Julius Werner <jwerner@chromium.org> | 2018-08-30 16:29:31 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2018-08-31 20:01:24 +0000 |
| commit | 3dd4953ac1fb4acfea410346efea8e8d62a21ea7 (patch) | |
| tree | 0bd2d1e0d653d5c68ed7147db22bc289889d2a71 /src/mainboard/google/cheza | |
| parent | 672f56166db97bf4ad2391db02303b88b413c791 (diff) | |
google/cheza: Adjust FMAP to fit new requirements
This patch overhauls the Cheza FMAP, removing some sections we don't
seem to need (RW_CDT, the two RW_XBL_BUFFERs, and the second copy of
RW_DDR_TRAINING), and adding new sections we're going to need soon or
should have had anyway (RO_DDR_TRAINING, RO_FSG, RW_LEGACY).
Make more use of implicit offsets and sizes, because we can and because
it should make future adjustments easier.
Change-Id: I0bd9e59e9cfa162c478c4bd1f048fcac61ad5062
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: T Michael Turney <mturney@codeaurora.org>
Diffstat (limited to 'src/mainboard/google/cheza')
| -rw-r--r-- | src/mainboard/google/cheza/chromeos.fmd | 57 |
1 files changed, 29 insertions, 28 deletions
diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index 29f16326ac..861b9b7e72 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -13,40 +13,41 @@ ## GNU General Public License for more details. ## -FLASH@0x0 0x800000 { - WP_RO@0x0 0x300000 { - RO_SECTION@0x0 0x2E0000 { - BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x1E0000 - FMAP@0x200000 0x1000 - GBB@0x201000 0xDEF00 - RO_FRID@0x2DFF00 0x100 +FLASH@0x0 8M { + WP_RO 4M { + RO_SECTION 0x184000 { + BOOTBLOCK 96K + COREBOOT(CBFS) + #TODO: Move FMAP to 2M or 3M once FSG can be smaller + FMAP@0x180000 0x1000 + GBB 0x2f00 + RO_FRID 0x100 } - RO_VPD@0x2E0000 0x2000 + RO_VPD 16K + RO_DDR_TRAINING 8K + RO_FSG } - RW_NVRAM@0x300000 0x8000 - RW_ELOG@0x308000 0x8000 - RW_VPD@0x310000 0x8000 - RW_CDT@0x318000 0x8000 - - RW_SECTION_A@0x320000 0x268000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x1E1F00 - RW_FWID_A@0x1E3F00 0x100 - RW_DDR_TRAINING_A@0x1E4000 0x4000 - RW_XBL_BUFFER_A@0x1E8000 0x4000 + RW_VPD 32K + RW_NVRAM 16K + RW_DDR_TRAINING 8K + RW_ELOG 4K + RW_SHARED 4K { + SHARED_DATA } - RW_SHARED@0x588000 0x10000 { - SHARED_DATA@0x0 0x10000 + RW_SECTION_A 1280K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 } - RW_SECTION_B@0x598000 0x268000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x1E1F00 - RW_FWID_B@0x1E3F00 0x100 - RW_DDR_TRAINING_B@0x1E4000 0x4000 - RW_XBL_BUFFER_B@0x1E8000 0x4000 + + RW_SECTION_B 1280K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 } + + RW_LEGACY(CBFS) } |