diff options
| author | T Michael Turney <mturney@codeaurora.org> | 2019-03-21 14:20:52 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2019-05-03 21:59:16 +0000 |
| commit | bd0b51c0be1ec2c9a5f02de3c13108c13941e2c2 (patch) | |
| tree | 38ebe5c50efb4d68ed65791670a61481c6cd9fee /src/mainboard/google/cheza/romstage.c | |
| parent | 101098c41a047184e3eceabca2c1baa11141f36e (diff) | |
sdm845: Add QCLib to RomStage to perform IP init
CB acts as I/O handler for QCLib (e.g. DDR training data)
This interface allows bi-directional data flow between
CB and QCLib
Tested and working interfaces:
DDR Training data
QCLib serial console output
DDR Information (base & size)
limits cfg data
TEST=build & run
Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/cheza/romstage.c')
| -rw-r--r-- | src/mainboard/google/cheza/romstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c index 7b7da4ce8c..de737b1159 100644 --- a/src/mainboard/google/cheza/romstage.c +++ b/src/mainboard/google/cheza/romstage.c @@ -15,6 +15,7 @@ #include <arch/stages.h> #include <soc/usb.h> +#include <soc/qclib_common.h> static void prepare_usb(void) { @@ -28,4 +29,7 @@ static void prepare_usb(void) void platform_romstage_main(void) { prepare_usb(); + + /* QCLib: DDR init & train */ + qclib_load_and_run(); } |