diff options
| author | Johnson Wang <johnson.wang@mediatek.corp-partner.google.com> | 2022-08-30 16:56:43 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-07 09:19:38 +0000 |
| commit | 70f30afa89b725aa8655bed881f823408ac54453 (patch) | |
| tree | 4852565596abcaee50dd999a949872fbad634ed1 /src/mainboard/google/cherry/mainboard.c | |
| parent | 60ef19bcf38bb5311d517c809c424b226d7ad1c4 (diff) | |
soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes
Some of the pll settings are incorrect, which cause problems in GPU
after booting into kernel.
- MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix
it to enable MFGPLL properly.
- Switch SPMI clock muxes to 260M to avoid kernel hang while probing
SPMI kernel driver.
TEST=GPU bringup correctly.
BUG=b:233720142
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Diffstat (limited to 'src/mainboard/google/cherry/mainboard.c')
0 files changed, 0 insertions, 0 deletions