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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2021-05-20 18:16:34 +0530
committerFelix Held <felix-coreboot@felixheld.de>2021-08-28 17:39:54 +0000
commitf032221bd1486c6c04bb19ad202bb5c6b525f8b0 (patch)
tree82a7b44063c516419afd886706c7362b58d262a9 /src/mainboard/google/brya
parent4b53474d2396a46c44e0627363777a2baf11e713 (diff)
mb/google/brya: Add two sensors for DPTF functionality
Add two thermal sensors for fan and wwan for DPTF based thermal control. BRANCH=None BUG=b:181271666 TEST=None Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
Diffstat (limited to 'src/mainboard/google/brya')
-rw-r--r--src/mainboard/google/brya/variants/brya0/overridetree.cb24
1 files changed, 21 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 9b451541be..d032a047b9 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -46,8 +46,10 @@ chip soc/intel/alderlake
device ref dtt on
chip drivers/intel/dptf
## sensor information
- register "options.tsr[0].desc" = ""DRAM""
- register "options.tsr[1].desc" = ""Charger""
+ register "options.tsr[0].desc" = ""DRAM_SOC""
+ register "options.tsr[1].desc" = ""Ambient""
+ register "options.tsr[2].desc" = ""Charger""
+ register "options.tsr[3].desc" = ""WWAN""
# TODO: below values are initial reference values only
## Active Policy
@@ -58,6 +60,18 @@ chip soc/intel/alderlake
TEMP_PCT(85, 90),
TEMP_PCT(80, 80),
TEMP_PCT(75, 70),
+ TEMP_PCT(70, 50),
+ TEMP_PCT(65, 30),
+ }
+ },
+ [1] = {
+ .target = DPTF_TEMP_SENSOR_1,
+ .thresholds = {
+ TEMP_PCT(50, 90),
+ TEMP_PCT(48, 70),
+ TEMP_PCT(46, 60),
+ TEMP_PCT(43, 40),
+ TEMP_PCT(40, 30),
}
}
}"
@@ -66,7 +80,9 @@ chip soc/intel/alderlake
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
- [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
+ [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
+ [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
+ [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
}"
## Critical Policy
@@ -74,6 +90,8 @@ chip soc/intel/alderlake
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+ [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
}"
register "controls.power_limits" = "{