diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-08-31 10:57:18 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-09-01 04:58:51 +0000 |
| commit | b1ae6ca7ef8b848e53577cb9da46c19d2d5886a8 (patch) | |
| tree | 8900b50b15d8934d7a1d8efc711ca8e7498ffe0d /src/mainboard/google/brya | |
| parent | f3d54feef4c700991dd11b012f810162c5b6b06a (diff) | |
tree: Use boolean for s0ix_enable
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/brya')
6 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 38535a4773..2ba54bcf11 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 0290181714..e07cf2adec 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index 4372888ebc..f91b0885ae 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index aac4bca376..3d28ed3e3d 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -29,7 +29,7 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index ffc3a56660..ad5b94328d 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -24,7 +24,7 @@ chip soc/intel/alderlake register "pmc_gpe0_dw2" = "GPP_F" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index a5b346c42f..868342b5ce 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -24,7 +24,7 @@ chip soc/intel/alderlake register "pmc_gpe0_dw2" = "GPP_F" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" |