diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-08-17 13:35:53 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-19 13:53:04 +0000 |
| commit | 923a403dcf1e0a42a62c9afd5b9ac2d5d321d960 (patch) | |
| tree | 323300667c19b636d2709c894f609cfb5cf08f4e /src/mainboard/google/brya | |
| parent | c0c477741d0089fb1eb83e4c88b6ad5ba1661cb9 (diff) | |
mb/google/brya: set tcc_offset value to 10
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature. This value is suggested by
Thermal team.
BUGb=b:195706434
BRANCH=None
TEST=Built for brya platform and verified the MSR value
Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 3281902464..762aa84bbe 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,6 +19,8 @@ chip soc/intel/alderlake # DPTF enable register "dptf_enable" = "1" + register "tcc_offset" = "10" # TCC of 90 + # Enable heci communication register "HeciEnabled" = "1" |