diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-06-09 13:24:15 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-07 13:48:19 +0000 |
| commit | 7c2514fc072f95eed6483518811fb6c39f780f5b (patch) | |
| tree | 13e9f0356150cf6b2ca6cb02c2ab761a2f2ad181 /src/mainboard/google/brya | |
| parent | e88989a5d42cf306b37e3d7c78013475c8338578 (diff) | |
mb/google/brya: Change GPP_F17 programming
Currently the EC's MKBP interrupt line is programmed as dual-routed to
both SCI and IOAPIC. The brya EC will pulse the MKBP GPIO and also
send a host event when there is an MKBP event for host to service.
This causes an extra SCI to be generated, and the kernel will respond
to each MKBP event with an extra unnecessary host command. Changing
the pad configuration for the MKBP GPIO to APIC only fixes this issue.
BUG=b:236706977
BRANCH=firmware-brya-14505.B
TEST=excess GET_NEXT_EVENT host commands are gone from EC log
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic7dd596987f6d34c69d46674bdd07785235e2d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65480
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index fb7bc21d2d..8b62f3c4db 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -246,7 +246,7 @@ static const struct pad_config gpio_table[] = { /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), + PAD_CFG_GPI_APIC_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */ |