diff options
| author | Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> | 2022-05-18 20:17:40 +0530 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-06-02 15:59:36 +0000 |
| commit | 596d5bc0fde61304d41b8bb2f1694371a498f00f (patch) | |
| tree | 6abf2bca462191f7db280984bff96c19102a57ca /src/mainboard/google/brya | |
| parent | 60c519ee875ec00554869a3f0218b40409f6c974 (diff) | |
soc/intel/alderlake: add power limits for Alder Lake-N SKUs
This patch adds support for the ADL-N SKUs based on the PCH ID.
Document reference: 645548 (ADL-N EDS Volume 1).
BUG=None
BRANCH=None
TEST=Build FW and test on adln_rvp board
Change-Id: I24c18a27a4a2c68c78bc3dc728c45ba04f57205d
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64472
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/brya')
0 files changed, 0 insertions, 0 deletions