mb/google/brya/var/nova: Add initial configurations

Upload initial configuration for nova based on proto schematics.

Memory:
SAMSUNG 2G*4 K4U6E3S4AB-MGCL
HYNIX 2G*4 H9HCNNNBKMMLXR-NEE

BUG=b:328711879
TEST=FW_NAME=nova emerge-constitution coreboot chromeos-bootimage

Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>

6 files changed, 551 insertions, 1 deletions

diff --git a/src/mainboard/google/brya/variants/nova/Makefile.mk b/src/mainboard/google/brya/variants/nova/Makefile.mk
new file mode 100644
index 0000000000..d38141ca24
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nova/Makefile.mk
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/nova/gpio.c b/src/mainboard/google/brya/variants/nova/gpio.c
new file mode 100644
index 0000000000..6ed8823faa
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nova/gpio.c
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A14 : USB_OC1# ==> NC */
+	PAD_NC(GPP_A14, NONE),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC(GPP_A15, NONE),
+	/* A19 : DDSP_HPD1 ==> NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	/* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+	/* B15 : TIME_SYNC0 ==> HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, EDGE_BOTH),
+	/* B16 : I2C5_SDA ==> PCH_I2C_TPU_SDA */
+	PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
+	/* B17 : I2C5_SCL ==> PCH_I2C_TPU_SCL */
+	PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
+
+	/* C0 : SMBCLK ==> NC */
+	PAD_NC(GPP_C0, NONE),
+	/* C1 : SMBDATA ==> NC */
+	PAD_NC(GPP_C1, NONE),
+	/* C3 : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4 : SML0DATA ==> SMBUS_ISP_SCALAR */
+	PAD_CFG_GPO(GPP_C4, 0, DEEP),
+
+	/* D0  : ISH_GP0 ==> BOOT_SEL_N */
+	PAD_NC(GPP_D0, NONE),
+	/* D1  : ISH_GP1 ==> REC_MODE */
+	PAD_NC(GPP_D1, NONE),
+	/* D2  : ISH_GP2 ==> DEV_MODE_CTRL */
+	PAD_NC(GPP_D2, NONE),
+	/* D3  : ISH_GP3 ==> BOOT_IND */
+	PAD_NC(GPP_D3, NONE),
+	/* D9  : ISH_SPI_CS# ==> NC */
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
+	/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG),
+	/* D13 : ISH_UART0_RXD ==> NC */
+	PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
+	/* D15 : ISH_UART0_RTS# ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_D15, 1, DEEP),
+	/* D16 : ISH_UART0_CTS# ==> USI_INT */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
+	/* D17 : UART1_RXD ==> PCH_RX_TSUM_UART_TX */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* D18 : UART1_TXD ==> PCH_TX_TSUM_UART_RX */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+
+	/* E4  : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+	PAD_CFG_GPI_LOCK(GPP_E4, NONE, LOCK_CONFIG),
+	/* E5  : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */
+	PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
+	/* E9  : USB_OC0# ==> USB_C0_OC_ODL */
+	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
+	/* E18 : DDP1_CTRLCLK ==> NC */
+	PAD_NC(GPP_E18, NONE),
+	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E19, NONE, LOCK_CONFIG),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC(GPP_E20, NONE),
+	/* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E21, NONE, LOCK_CONFIG),
+
+	/* F11 : THC1_SPI2_CLK ==> MEM_CH_SEL */
+	PAD_CFG_GPI_LOCK(GPP_F11, NONE, LOCK_CONFIG),
+	/* F12 : GSXDOUT ==> MEM_STRAP_1 */
+	PAD_CFG_GPI_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* F13 : GSXDOUT ==> MEM_STRAP_2 */
+	PAD_CFG_GPI_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> MEM_STRAP_3 */
+	PAD_CFG_GPI_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* F16 : GSXCLK ==> MEM_STRAP_0 */
+	PAD_CFG_GPI_LOCK(GPP_F16, NONE, LOCK_CONFIG),
+
+	/* H12 : I2C7_SDA ==> NC */
+	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
+	/* H13 : I2C7_SCL ==> NC */
+	PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
+	/* H15 : DDPB_CTRLCLK ==> NC */
+	PAD_NC(GPP_H15, NONE),
+	/* H17 : DDPB_CTRLDATA ==> NC */
+	PAD_NC(GPP_H17, NONE),
+	/* H19 : SRCCLKREQ4# ==> M2_TPU1_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+
+	/* R0 : HDA_BCLK ==> NC */
+	PAD_NC_LOCK(GPP_R0, NONE, LOCK_CONFIG),
+	/* R1 : HDA_SYNC ==> I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_R1, NONE, LOCK_CONFIG),
+	/* R2 : HDA_SDO ==> NC */
+	PAD_NC(GPP_R2, NONE),
+	/* R3 : HDA_SDIO ==> NC */
+	PAD_NC(GPP_R3, NONE),
+	/* R4 : HDA_RST# ==> NC */
+	PAD_NC(GPP_R4, NONE),
+	/* R5 : HDA_SDI1 ==> NC */
+	PAD_NC(GPP_R5, NONE),
+	/* R6 : I2S2_TXD ==> NC */
+	PAD_NC(GPP_R6, NONE),
+	/* R7 : I2S2_RXD ==> NC */
+	PAD_NC(GPP_R7, NONE),
+
+	/* S0 : SNDW0_CLK ==> PCH_I2S_SCLK_MX8M */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
+	/* S1 : SNDW0_DATA ==> PCH_I2S_SFRM_MX8M */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
+	/* S2 : SNDW1_CLK ==> PCH_I2S_TX_MX8M_RX */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
+	/* S3 : SNDW1_DATA ==> PCH_I2S_RX_MX8M_TX */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F14 : GSXDIN ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/nova/memory/Makefile.mk b/src/mainboard/google/brya/variants/nova/memory/Makefile.mk
new file mode 100644
index 0000000000..bb0957dfe2
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nova/memory/Makefile.mk
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-1/spd-3.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL
diff --git a/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..e2089db069
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+K4U6E3S4AB-MGCL                0 (0000)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+MT53E1G32D2NP-046 WT:B         1 (0001)
+K4UBE3D4AB-MGCL                1 (0001)
diff --git a/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..10f244d15b
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
@@ -0,0 +1,4 @@
+K4U6E3S4AB-MGCL
+H9HCNNNBKMMLXR-NEE
+MT53E1G32D2NP-046 WT:B
+K4UBE3D4AB-MGCL
diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb
index 4f2c04a57a..93018ea074 100644
--- a/src/mainboard/google/brya/variants/nova/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nova/overridetree.cb
@@ -1,6 +1,333 @@
 chip soc/intel/alderlake
+	register "domain_vr_config[VR_DOMAIN_IA]" = "{
+		.enable_fast_vmode = 1,
+	}"
 
-        device domain 0 on
+	register "sagv" = "SaGv_Enabled"
+
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 5
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 6
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 7
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 8
+
+	register "usb3_ports[0]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A2
+	register "usb3_ports[1]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A3
+
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"	# Disable Type-A port
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# Disable Type-A port
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | Scaler                    |
+	#| I2C1              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C2              | HDMI_A                    |
+	#| I2C3              | Touchscreen               |
+	#| I2C5              | TPU                       |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""Charger""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on end	# Scaler
+		device ref i2c1 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end	#TPM
+		device ref i2c2 on end	# HDMI_A
+		device ref i2c3 on
+			chip drivers/i2c/hid
+                                register "generic.hid" = ""ILTK0001""
+                                register "generic.desc" = ""ILITEK Touchscreen""
+                                register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
+                                register "generic.detect" = "1"
+                                register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+                                register "generic.reset_delay_ms" = "200"
+                                register "generic.enable_delay_ms" = "12"
+                                register "generic.has_power_resource" = "1"
+                                register "hid_desc_reg_offset" = "0x01"
+                                device i2c 41 on end
+			end
+		end	# Touch screen
+		device ref i2c5 on end	# TPU
+		device ref pcie_rp6 on
+			# Enable PCIE 6 using clk 3
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end #TPU0
+		device ref pcie_rp7 on
+			# Enable PCIE 7 using clk 6
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/net
+				register "customized_leds" = "0x05af"
+				register "wake" = "GPE0_DW0_07"	# GPP_A7
+				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
+				device pci 00.0 on end
+			end
+		end # RTL8111H Ethernet NIC
+		device ref pcie_rp8 on
+			# Enable PCIE 8 using clk 4
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end #TPU1
+		device ref uart0 on end
+		device ref uart1 on end
+		device ref gspi0 off end
+		device ref gspi1 off end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(0, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(0, 0))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(0, 0))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(0, 1))"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
         end
 
 end