diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2021-08-10 15:13:15 +0600 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-12 17:51:04 +0000 |
| commit | 09a32863dada661af6cdafc2914daac93924ac8b (patch) | |
| tree | 80d2f6bf9feda699146f249f228fb0fbe5082eac /src/mainboard/google/brya | |
| parent | 155ae1bd1c4272ead2862990d7566d58bc371da0 (diff) | |
mb/google/brya/variants/redrix: enable LTE PCIe port
Enable LTE PCIe port according to fw config.
BUG=b:192052098
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: Ic9472d2249c622858a75c63bc82e8e4e8166a3d7
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56894
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/redrix/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index bd9fa32cf8..822db2eee3 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -142,6 +142,9 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref pcie_rp6 on + probe DB_LTE LTE_PCIE + end device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" |