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authorTerry Chen <terry_chen@wistron.corp-partner.google.com>2022-05-03 18:23:25 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-05-05 14:20:24 +0000
commitf8042458f789a6cb583802319b9bcd49bad66ed7 (patch)
treef9a5d6575661c934ad55af57247127e3133287d2 /src/mainboard/google/brya/variants
parent7ef5158c7db3e1872861fe09ea147f0511099630 (diff)
mb/google/brya/var/crota: setting for codec reset pin
Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
-rw-r--r--src/mainboard/google/brya/variants/crota/gpio.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c
index a5464552f4..35803a0242 100644
--- a/src/mainboard/google/brya/variants/crota/gpio.c
+++ b/src/mainboard/google/brya/variants/crota/gpio.c
@@ -22,8 +22,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> NC */
PAD_NC(GPP_B3, NONE),
- /* B15 : TIME_SYNC0 ==> NC */
- PAD_NC(GPP_B15, NONE),
+ /* B15 : PROC_GP3 ==> AUD_RST_L */
+ PAD_CFG_GPO(GPP_B15, 1, PWROK),
/* C3 : GPP_C3 ==> SML0_SMBCLK */
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),