diff options
| author | Ian Feng <ian_feng@compal.corp-partner.google.com> | 2023-01-05 10:09:15 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-01-09 00:25:54 +0000 |
| commit | d5d6ecf63a87eb110f74dae9aa542eb9ee1872a8 (patch) | |
| tree | dc0fb53bd8b4ad8e8f461d7dcec02f0118316687 /src/mainboard/google/brya/variants | |
| parent | c28382eda24164ae5d50b80e8ba8977e8072b616 (diff) | |
mb/google/nissa/var/xivu: Update DPTF parameters
Follow thermal table from thermal team.
1. Enable TS3 thermal sensor.
2. Set TS3 passive policy to 63.
3. Set TS3 critical policy to 73.
4. Modify TSR2 passive policy to CPU.
BUG=b:263554342
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ia1fcaee15a8b58b755ce0a48a1978e795b66efd7
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71658
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/xivu/overridetree.cb | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index bfaa639f41..e98750cd3c 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -145,7 +145,8 @@ chip soc/intel/alderlake ## sensor information register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Ambient"" - register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[2].desc" = ""ChargerMB"" + register "options.tsr[3].desc" = ""ChargerSUB"" # TODO: below values are initial reference values only ## Passive Policy @@ -153,7 +154,8 @@ chip soc/intel/alderlake [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 77, 5000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 68, 5000), - [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 78, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 78, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 63, 5000), }" ## Critical Policy @@ -161,6 +163,7 @@ chip soc/intel/alderlake [0] = DPTF_CRITICAL(TEMP_SENSOR_0, 87, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_1, 78, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_2, 88, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_3, 73, SHUTDOWN), }" register "controls.power_limits" = "{ |