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authorIan Feng <ian_feng@compal.corp-partner.google.com>2022-11-24 10:49:35 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-11-25 16:41:57 +0000
commitc6e6d0d522f208b0d2ee08d108ea50d15ab109cd (patch)
treeaa00500c3c33cf997982e0084324d18696586a9b /src/mainboard/google/brya/variants
parent68fb5437f9680428cbb7cf39c4a73911671a6359 (diff)
mb/google/nissa/var/xivu: Update DPTF parameters
Follow thermal table from thermal team. 1. Modify TS1 passive policy to 68. BUG=b:249446156 TEST=emerge-nissa coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
-rw-r--r--src/mainboard/google/brya/variants/xivu/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb
index 0c8ed39b3b..ac23c68517 100644
--- a/src/mainboard/google/brya/variants/xivu/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb
@@ -107,7 +107,7 @@ chip soc/intel/alderlake
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 77, 5000),
- [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000),
+ [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 68, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 78, 5000),
}"