mb/google/nissa: Add gpio lock pins

Followed the Brya series to lock the gpio pins in baseboard. Variant
should honor locked gpios from baseboard, but not the last. Variant can
add more gpios to lock if needed.

BUG=b:216671701
TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that
nivviks boots successfully to kernel.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 48 insertions, 48 deletions

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
index 06fc1b714a..ba3c8c5006 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
@@ -29,13 +29,13 @@ static const struct pad_config gpio_table[] = {
 	/* A12 : NC */
 	PAD_NC(GPP_A12, NONE),
 	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* A14 : USB_OC1# ==> NC */
 	PAD_NC(GPP_A14, NONE),
 	/* A15 : USB_OC2# ==> NC */
 	PAD_NC(GPP_A15, NONE),
 	/* A16 : USB_OC3# ==> NC */
-	PAD_NC(GPP_A16, NONE),
+	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
 	/* A17 : NC */
 	PAD_NC(GPP_A17, NONE),
 	/* A18 : NC */
@@ -58,17 +58,17 @@ static const struct pad_config gpio_table[] = {
 	/* B2  : NC */
 	PAD_NC(GPP_B2, NONE),
 	/* B3  : NC */
-	PAD_NC(GPP_B3, NONE),
+	PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
 	/* B4  : NC */
-	PAD_NC(GPP_B4, NONE),
+	PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
 	/* B5  : I2C2_SDA ==> SOC_I2C_SUB_SDA */
-	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
 	/* B6  : I2C2_SCL ==> SOC_I2C_SUB_SCL */
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
 	/* B7  : I2C3_SDA ==> SOC_I2C_AUDIO_SDA */
-	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
 	/* B8  : I2C3_SCL ==> SOC_I2C_AUDIO_SCL */
-	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
 	/* B9  : Not available */
 	PAD_NC(GPP_B9, NONE),
 	/* B10 : Not available */
@@ -80,13 +80,13 @@ static const struct pad_config gpio_table[] = {
 	/* B13 : PLTRST# ==> PLT_RST_L */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14 : SPKR ==> GPP_B14_STRAP */
-	PAD_NC(GPP_B14, NONE),
+	PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG),
 	/* B15 : NC */
-	PAD_NC(GPP_B15, NONE),
+	PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
 	/* B16 : I2C5_SDA ==> SOC_I2C_TCHPAD_SDA */
-	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
 	/* B17 : I2C5_SCL ==> SOC_I2C_TCHPAD_SCL */
-	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
 	/* B18 : GPP_B18 ==> GPP_B18_STRAP */
 	PAD_NC(GPP_B18, NONE),
 	/* B19 : Not available */
@@ -118,13 +118,13 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
 
 	/* D0  : NC */
-	PAD_NC(GPP_D0, NONE),
+	PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
 	/* D1  : NC */
-	PAD_NC(GPP_D1, NONE),
+	PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
 	/* D2  : NC */
-	PAD_NC(GPP_D2, NONE),
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
 	/* D3  : ISH_GP3 ==> WCAM_RST_L */
-	PAD_CFG_GPO(GPP_D3, 0, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
 	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_D4, 1, DEEP),
 	/* D5  : NC */
@@ -136,34 +136,34 @@ static const struct pad_config gpio_table[] = {
 	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 	/* D9  : NC */
-	PAD_NC(GPP_D9, NONE),
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
 	/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
-	PAD_NC(GPP_D10, NONE),
+	PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
 	/* D11 : NC */
-	PAD_NC(GPP_D11, NONE),
+	PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
 	/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
-	PAD_NC(GPP_D12, NONE),
+	PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
 	/* D13 : NC */
-	PAD_NC(GPP_D13, NONE),
+	PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
 	/* D14 : NC */
-	PAD_NC(GPP_D14, NONE),
+	PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
 	/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
-	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
 	/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
-	PAD_CFG_GPO(GPP_D16, 0, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG),
 	/* D17 : NC */
-	PAD_NC(GPP_D17, NONE),
+	PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
 	/* D18 : NC */
-	PAD_NC(GPP_D18, NONE),
+	PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
 	/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
 	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 
 	/* E0  : NC */
 	PAD_NC(GPP_E0, NONE),
 	/* E1  : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
-	PAD_CFG_GPI(GPP_E1, NONE, DEEP),
+	PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
 	/* E2  : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
-	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
 	/* E3  : PROC_GP0 ==> MEM_STRAP_2 */
 	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
 	/* E4  : NC */
@@ -171,21 +171,21 @@ static const struct pad_config gpio_table[] = {
 	/* E5  : NC */
 	PAD_NC(GPP_E5, NONE),
 	/* E6  : THC0_SPI1_RST# ==> GPP_E6_STRAP */
-	PAD_NC(GPP_E6, NONE),
+	PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
 	/* E7  : NC */
 	PAD_NC(GPP_E7, NONE),
 	/* E8  : GPP_E8 ==> WLAN_DISABLE_L */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9  : NC */
-	PAD_NC(GPP_E9, NONE),
+	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
 	/* E10 : NC */
-	PAD_NC(GPP_E10, NONE),
+	PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 	/* E11 : NC */
-	PAD_NC(GPP_E11, NONE),
+	PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
-	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
 	/* E13 : NC */
-	PAD_NC(GPP_E13, NONE),
+	PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 	/* E14 : DDSP_HPDA ==> EDP_HPD */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15 : NC */
@@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
 	/* E16 : NC */
 	PAD_NC(GPP_E16, NONE),
 	/* E17 : NC */
-	PAD_NC(GPP_E17, NONE),
+	PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 	/* E18 : NC */
 	PAD_NC(GPP_E18, NONE),
 	/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
@@ -230,21 +230,21 @@ static const struct pad_config gpio_table[] = {
 	/* F10 : GPP_F10 ==> GPP_F10_STRAP */
 	PAD_NC(GPP_F10, NONE),
 	/* F11 : NC */
-	PAD_NC(GPP_F11, NONE),
+	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 	/* F12 : GSXDOUT ==> WWAN_RST_L */
-	PAD_CFG_GPO(GPP_F12, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
 	/* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */
-	PAD_CFG_GPI_GPIO_DRIVER(GPP_F13, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 	/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
-	PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, DEEP, EDGE_SINGLE),
+	PAD_CFG_GPI_SCI_HIGH_LOCK(GPP_F15, NONE, EDGE_SINGLE, LOCK_CONFIG),
 	/* F16 : NC */
-	PAD_NC(GPP_F16, NONE),
+	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 	/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
-	PAD_CFG_GPI_SCI(GPP_F17, NONE, DEEP, LEVEL, INVERT),
+	PAD_CFG_GPI_SCI_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
 	/* F19 : Not available */
 	PAD_NC(GPP_F19, NONE),
 	/* F20 : Not available */
@@ -263,11 +263,11 @@ static const struct pad_config gpio_table[] = {
 	/* H2  : GPP_H2_STRAP */
 	PAD_NC(GPP_H2, NONE),
 	/* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
-	PAD_CFG_GPI_SCI_LOW(GPP_H3, NONE, DEEP, EDGE_SINGLE),
+	PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
 	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
 	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
 	/* H6  : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
 	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 	/* H7  : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
@@ -281,9 +281,9 @@ static const struct pad_config gpio_table[] = {
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 	/* H12 : UART0_RTS# ==> SD_PERST_L */
-	PAD_CFG_GPO(GPP_H12, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_H12, 1, LOCK_CONFIG),
 	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
-	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
 	/* H14 : Not available */
 	PAD_NC(GPP_H14, NONE),
 	/* H15 : NC */