mb/google/var/taniks: Add gpios to lock

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
taniks boots successfully to kernel.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icf6cb0d057f9ad3cbcc1155423ed7efa58a46d0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 20 insertions, 20 deletions

diff --git a/src/mainboard/google/brya/variants/taniks/gpio.c b/src/mainboard/google/brya/variants/taniks/gpio.c
index 05a68d1777..0d36fc2c16 100644
--- a/src/mainboard/google/brya/variants/taniks/gpio.c
+++ b/src/mainboard/google/brya/variants/taniks/gpio.c
@@ -33,9 +33,9 @@ static const struct pad_config override_gpio_table[] = {
 	/* B2  : VRALERT# ==> NC */
 	PAD_NC(GPP_B2, NONE),
 	/* B3  : PROC_GP2 ==> NC */
-	PAD_NC(GPP_B3, NONE),
+	PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
 	/* B15 : TIME_SYNC0 ==> NC */
-	PAD_NC(GPP_B15, NONE),
+	PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
 
 	/* C3 : SML0CLK ==> NC */
 	PAD_NC(GPP_C3, NONE),
@@ -45,27 +45,27 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC(GPP_C6, NONE),
 
 	/* D1  : ISH_GP1 ==> NC */
-	PAD_NC(GPP_D1, NONE),
+	PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
 	/* D2  : ISH_GP2 ==> NC */
-	PAD_NC(GPP_D2, NONE),
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
 	/* D3  : ISH_GP3 ==> NC */
-	PAD_NC(GPP_D3, NONE),
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
 	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 	/* D9  : ISH_SPI_CS# ==> NC */
-	PAD_NC(GPP_D9, NONE),
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
 	/* D10 : ISH_SPI_CLK ==> NC */
-	PAD_NC(GPP_D10, NONE),
+	PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
 	/* D13 : ISH_UART0_RXD ==> NC */
-	PAD_NC(GPP_D13, NONE),
+	PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
 	/* D14 : ISH_UART0_TXD ==> NC */
-	PAD_NC(GPP_D14, NONE),
+	PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
 	/* D15 : ISH_UART0_RTS# ==> NC */
-	PAD_NC(GPP_D15, NONE),
+	PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
 	/* D16 : ISH_UART0_CTS# ==> NC */
-	PAD_NC(GPP_D16, NONE),
+	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
 	/* D17 : UART1_RXD ==> NC */
-	PAD_NC(GPP_D17, NONE),
+	PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
 
 	/* E0  : SATAXPCIE0 ==> NC */
 	PAD_NC(GPP_E0, NONE),
@@ -78,11 +78,11 @@ static const struct pad_config override_gpio_table[] = {
 	/* E7  : PROC_GP1 ==> NC */
 	PAD_NC(GPP_E7, NONE),
 	/* E10 : THC0_SPI1_CS# ==> NC */
-	PAD_NC(GPP_E10, NONE),
+	PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 	/* E16 : RSVD_TP ==> NC */
 	PAD_NC(GPP_E16, NONE),
 	/* E17 : THC0_SPI1_INT# ==> NC */
-	PAD_NC(GPP_E17, NONE),
+	PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 	/* E18 : DDP1_CTRLCLK ==> NC */
 	PAD_NC(GPP_E18, NONE),
 	/* E19 : DDP1_CTRLDATA ==> NC */
@@ -95,15 +95,15 @@ static const struct pad_config override_gpio_table[] = {
 	/* F6  : CNV_PA_BLANKING ==> NC */
 	PAD_NC(GPP_F6, NONE),
 	/* F11 : THC1_SPI2_CLK ==> NC */
-	PAD_NC(GPP_F11, NONE),
+	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 	/* F12 : GSXDOUT ==> NC */
-	PAD_NC(GPP_F12, NONE),
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 	/* F13 : GSXDOUT ==> NC */
-	PAD_NC(GPP_F13, NONE),
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 	/* F15 : GSXSRESET# ==> NC */
-	PAD_NC(GPP_F15, NONE),
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 	/* F16 : GSXCLK ==> NC */
-	PAD_NC(GPP_F16, NONE),
+	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 	/* F19 : SRCCLKREQ6# ==> NC */
 	PAD_NC(GPP_F19, NONE),
 	/* F20 : EXT_PWR_GATE# ==> NC */
@@ -124,7 +124,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* H9  : I2C4_SCL ==> NC */
 	PAD_NC(GPP_H9, NONE),
 	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
-	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
 	/* H15 : DDPB_CTRLCLK ==> NC */
 	PAD_NC(GPP_H15, NONE),
 	/* H17 : DDPB_CTRLDATA ==> NC */