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authorMatt DeVillier <matt.devillier@gmail.com>2023-09-08 20:57:55 -0500
committerFelix Held <felix-coreboot@felixheld.de>2023-09-25 15:35:20 +0000
commit189da313f98145e1da43d8bc69ceeb4a97db7971 (patch)
tree0b8a036013fbf6f1698415707cc7d3e43858688f /src/mainboard/google/brya/variants/yavilla
parent7f53e11425b59f27e2fa70bab9daa3ca0a509177 (diff)
mb/google/brya: Add SOF driver entries for Nissa-based boards
Facilitates correct profile selection by SOF Windows drivers. Profiles for nokris and quandiso will be added once correct board configs can be determined. TEST=build/boot Win11 on google/craask, verify correct audio profiles loaded, audio functional. Change-Id: Id4582b5dd74a4905ea509813ec99663577360095 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/yavilla')
-rw-r--r--src/mainboard/google/brya/variants/yavilla/overridetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
index 6d2b47f918..8e8cf768b9 100644
--- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb
@@ -421,6 +421,12 @@ chip soc/intel/alderlake
register "sdmode_delay" = "5"
device generic 0 on end
end
+ chip drivers/sof
+ register "spkr_tplg" = "max98360a"
+ register "jack_tplg" = "rt5682"
+ register "mic_tplg" = "_2ch_pdm0"
+ device generic 0 on end
+ end
end
device ref pcie_rp4 on
# PCIe 4 WLAN