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authorFelix Held <felix-coreboot@felixheld.de>2022-04-02 04:06:12 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-04-03 17:07:08 +0000
commitc6b71bc6148eaa806edb2ad97eed864871da4d8c (patch)
treeaaaa16f2214a98029ee709c46769753fbc2e0072 /src/mainboard/google/brya/variants/vell
parent11b0d360ba20d452a993e5474dd41b538c85c5b5 (diff)
soc/amd/cezanne/fw.cfg: provide default SPL table binary
Chause doesn't get to x86 bootblock without the SPL table binary in the PSP directory table, so I assume that Majolica won't get to x86 bootblock either, since the Cezanne SoC default is not to include any SPL table binary. This was caused by a combination of commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table) that caused a regression in amdfwtool and commit c5b912f788765560c1db08f3341826b9c548b865 (soc/amd/cezanne: Allow to specify SPL table path in Kconfig) that removed the default for the Cezanne SoC. Fix this by adding the default SPL table file back to the fw.cfg file which will get ignored by amdfwtool when a mainboard selects SPL_TABLE_FILE and specifies another SPL table binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff Reviewed-on: https://review.coreboot.org/c/coreboot/+/61896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/vell')
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