mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix

This change is to move MPTS (Mainboard Prepare To Sleep) method from
wwan_power.asl to SSDT.

MPTS is mainboard-specific method, while wwan_power.asl is meant for
WWAN from its name.

Having fixed MPTS method (i.e. DSDT) can not cover the case where device
only presents and certain CBI bit(s) is(are) set.

In Redrix and Brya, there are SKUs with or without 5G, 4G device. For
those with 4G, MPTS method should be different. For those with no WWAN
device, no MPTS is needed.

Having MPTS generating in SSDT also eliminates the need for introducing
Kconfig flags to support different devices in the future.
MPTS method is created inside mainboard_fill_ssdt function in which the
corresponding variant function is called.

This will generate the following for the mainboard:
Scope (\_SB)
{
    Method (MPTS, 1, Serialized)
    {
        Local0 = \_SB.PCI0.RP01.RTD3._STA ()
        If ((Local0 == One))
        {
            \_SB.PCI0.RP01.PXSX.DPTS (Arg0)
        }
    }
}

Test:
Check the SSDT for MPTS method under \_SB after boot to OS
Use shutdown command and check the GPIO pins from logical analyzer

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 2 insertions, 1 deletions

diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 62a24eda68..2bf3fc23be 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -92,6 +92,7 @@ chip soc/intel/alderlake
 		},
 	}"
 	register "tcc_offset" = "3"  # TCC of 97C
+
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
@@ -178,7 +179,7 @@ chip soc/intel/alderlake
 				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 on
+				device generic 0 alias rp6_wwan on
 					probe DB_LTE LTE_PCIE
 				end
 			end