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authorArec Kao <arec.kao@intel.com>2021-09-16 12:03:45 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-09-16 20:46:41 +0000
commit093ac930322371a2d5cac5c262f1a95288653aa7 (patch)
treeed0b8047b23ac2fd03aa2752bfd59b014001e551 /src/mainboard/google/brya/variants/redrix
parent5c4783c205731410b1adee4c51b3019464ffbb3a (diff)
mb/google/brya/var/redrix: Select camera module based on SSFC value
This patch has changes to support multiple camera modules, base on the value set in the SSFC_CONFIG. BUG=b:198235323 TEST=tested the changes with redrix 5MP(ov5675/hi556) camera. Change-Id: I71c8355617171ec7d08862759b87d4bf12ce2924 Signed-off-by: Arec Kao <arec.kao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57272 Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/redrix')
-rw-r--r--src/mainboard/google/brya/variants/redrix/overridetree.cb53
1 files changed, 50 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 9f28dc2d42..67db30a4ad 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -20,6 +20,11 @@ fw_config
option PRIVACY_SCREEN_ABSENT 0
option PRIVACY_SCREEN 1
end
+ field CAMERA_UFC 38 39
+ option CAMERA_NONE 0
+ option CAMERA_OV5675 1
+ option CAMERA_HI556 2
+ end
end
chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled"
@@ -271,7 +276,7 @@ chip soc/intel/alderlake
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
- register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #PP3300_FCAM_X
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #EN_UCAM_LED_PWR
register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR
register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
@@ -289,7 +294,50 @@ chip soc/intel/alderlake
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
- device i2c 36 on end
+ device i2c 36 on
+ probe CAMERA_UFC CAMERA_NONE
+ probe CAMERA_UFC CAMERA_OV5675
+ end
+ end
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = ""INT3537""
+ register "acpi_uid" = "0"
+ register "acpi_name" = ""CAM0""
+ register "chip_name" = ""Hi-556 Camera""
+ register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+ register "ssdb.lanes_used" = "2"
+ register "ssdb.link_used" = "1"
+ register "num_freq_entries" = "1"
+ register "link_freq[0]" = "437000000"
+ register "remote_name" = ""IPU0""
+
+ register "has_power_resource" = "1"
+ #Controls
+ register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+ register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #EN_UCAM_LED_PWR
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR
+ register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
+
+ #_ON
+ register "on_seq.ops_cnt" = "5"
+ register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+ register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+ register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "4"
+ register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+ register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+ device i2c 20 on
+ probe CAMERA_UFC CAMERA_HI556
+ end
end
chip drivers/intel/mipi_camera
register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
@@ -305,7 +353,6 @@ chip soc/intel/alderlake
register "nvm_readonly" = "1"
register "nvm_width" = "0x10"
register "nvm_compat" = ""atmel,24c64""
-
device i2c 50 on end
end